Build Logs

1##################################

2Clonning https://github.com/dfianthdl/dfhdl.git into /build/repo using revision v0.16.0

3##################################

4Note: switching to 'b453bfec2949926e3a598e22a077b465b621fc59'.

6You are in 'detached HEAD' state. You can look around, make experimental

7changes and commit them, and you can discard any commits you make in this

8state without impacting any branches by switching back to a branch.

10If you want to create a new branch to retain commits you create, you may

11do so (now or later) by using -c with the switch command. Example:

13 git switch -c <new-branch-name>

15Or undo this operation with:

17 git switch -

19Turn off this advice by setting config variable advice.detachedHead to false

21----

22Preparing build for 3.8.0-RC4

23Scala binary version found: 3.8

24Implicitly using source version 3.8

25Scala binary version found: 3.8

26Implicitly using source version 3.8

27Would try to apply common scalacOption (best-effort, sbt/mill only):

28Append: ,REQUIRE:-source:3.8

29Remove: ,-deprecation,-feature,-Xfatal-warnings,-Werror,MATCH:.*-Wconf.*any:e

31Try apply source patch:

32Path: build.sbt

33Pattern: val compilerVersion = .*

34Replacement: val compilerVersion = "3.8.0-RC4"

35Starting compilation server

36Compiling project (Scala 3.7.3, JVM (17))

37Compiled project (Scala 3.7.3, JVM (17))

38Successfully applied pattern 'val compilerVersion = .*' in build.sbt

39----

40Starting build for 3.8.0-RC4

41Execute tests: true

42sbt project found:

43No prepare script found for project dfianthdl/dfhdl

44##################################

45Scala version: 3.8.0-RC4

46Targets: io.github.dfianthdl%dfhdl io.github.dfianthdl%dfhdl-compiler-ir io.github.dfianthdl%dfhdl-compiler-stages io.github.dfianthdl%dfhdl-core io.github.dfianthdl%dfhdl-internals io.github.dfianthdl%dfhdl-platforms

47Project projectConfig: {"projects":{"exclude":[],"overrides":{"dfhdl":{"tests":"compile-only"}}},"java":{"version":"17"},"sbt":{"commands":[],"options":[]},"mill":{"options":[]},"tests":"full","migrationVersions":[],"sourcePatches":[{"path":"build.sbt","pattern":"val compilerVersion = .*","replaceWith":"val compilerVersion = \"<SCALA_VERSION>\""}]}

48##################################

49Using extra scalacOptions: ,REQUIRE:-source:3.8

50Filtering out scalacOptions: ,-deprecation,-feature,-Xfatal-warnings,-Werror,MATCH:.*-Wconf.*any:e

51[sbt_options] declare -a sbt_options=()

52[process_args] java_version = '17'

53[copyRt] java9_rt = '/root/.sbt/1.0/java9-rt-ext-eclipse_adoptium_17_0_8/rt.jar'

54# Executing command line:

55java

56-Dfile.encoding=UTF-8

57-Dcommunitybuild.scala=3.8.0-RC4

58-Dcommunitybuild.project.dependencies.add=

59-Xmx7G

60-Xms4G

61-Xss8M

62-Dsbt.script=/root/.sdkman/candidates/sbt/current/bin/sbt

63-Dscala.ext.dirs=/root/.sbt/1.0/java9-rt-ext-eclipse_adoptium_17_0_8

64-jar

65/root/.sdkman/candidates/sbt/1.11.5/bin/sbt-launch.jar

66"setCrossScalaVersions 3.8.0-RC4"

67"++3.8.0-RC4 -v"

68"mapScalacOptions ",REQUIRE:-source:3.8,-Wconf:msg=can be rewritten automatically under:s" ",-deprecation,-feature,-Xfatal-warnings,-Werror,MATCH:.*-Wconf.*any:e""

69"set every credentials := Nil"

70"excludeLibraryDependency com.github.ghik:zerowaste_{scalaVersion} com.olegpy:better-monadic-for_3 org.polyvariant:better-tostring_{scalaVersion} org.wartremover:wartremover_{scalaVersion}"

71"removeScalacOptionsStartingWith -P:wartremover"

73moduleMappings

74"runBuild 3.8.0-RC4 """{"projects":{"exclude":[],"overrides":{"dfhdl":{"tests":"compile-only"}}},"java":{"version":"17"},"sbt":{"commands":[],"options":[]},"mill":{"options":[]},"tests":"full","migrationVersions":[],"sourcePatches":[{"path":"build.sbt","pattern":"val compilerVersion = .*","replaceWith":"val compilerVersion = \"<SCALA_VERSION>\""}]}""" io.github.dfianthdl%dfhdl io.github.dfianthdl%dfhdl-compiler-ir io.github.dfianthdl%dfhdl-compiler-stages io.github.dfianthdl%dfhdl-core io.github.dfianthdl%dfhdl-internals io.github.dfianthdl%dfhdl-platforms"

76[info] [launcher] getting org.scala-sbt sbt 1.11.7 (this may take some time)...

77[info] welcome to sbt 1.11.7 (Eclipse Adoptium Java 17.0.8)

78[info] loading settings for project repo-build from akka.sbt, plugins.sbt...

79[info] loading project definition from /build/repo/project

80[info] loading settings for project root from build.sbt...

81[info] set current project to dfhdl (in build file:/build/repo/)

82Execute setCrossScalaVersions: 3.8.0-RC4

83OpenCB::Changing crossVersion 3.8.0-RC4 -> 3.8.0-RC4 in core/crossScalaVersions

84OpenCB::Changing crossVersion 3.8.0-RC4 -> 3.8.0-RC4 in plugin/crossScalaVersions

85OpenCB::Changing crossVersion 3.8.0-RC4 -> 3.8.0-RC4 in internals/crossScalaVersions

86OpenCB::Changing crossVersion 3.8.0-RC4 -> 3.8.0-RC4 in platforms/crossScalaVersions

87OpenCB::Changing crossVersion 3.8.0-RC4 -> 3.8.0-RC4 in lib/crossScalaVersions

88OpenCB::Changing crossVersion 3.8.0-RC4 -> 3.8.0-RC4 in compiler_ir/crossScalaVersions

89OpenCB::Changing crossVersion 3.8.0-RC4 -> 3.8.0-RC4 in compiler_stages/crossScalaVersions

90OpenCB::Changing crossVersion 3.8.0-RC4 -> 3.8.0-RC4 in root/crossScalaVersions

91[info] set current project to dfhdl (in build file:/build/repo/)

92[info] Setting Scala version to 3.8.0-RC4 on 8 projects.

93[info] Switching Scala version on:

94[info] plugin (3.8.0-RC4)

95[info] compiler_ir (3.8.0-RC4)

96[info] * root (3.8.0-RC4)

97[info] platforms (3.8.0-RC4)

98[info] lib (3.8.0-RC4)

99[info] internals (3.8.0-RC4)

100[info] core (3.8.0-RC4)

101[info] compiler_stages (3.8.0-RC4)

102[info] Excluding projects:

103[info] Reapplying settings...

104[info] set current project to dfhdl (in build file:/build/repo/)

105Execute mapScalacOptions: ,REQUIRE:-source:3.8,-Wconf:msg=can be rewritten automatically under:s ,-deprecation,-feature,-Xfatal-warnings,-Werror,MATCH:.*-Wconf.*any:e

106[info] Reapplying settings...

107[info] set current project to dfhdl (in build file:/build/repo/)

108[info] Defining Global / credentials, compiler_ir / credentials and 6 others.

109[info] The new values will be used by Global / pgpSelectPassphrase, Global / pgpSigningKey and 39 others.

110[info] Run `last` for details.

111[info] Reapplying settings...

112[info] set current project to dfhdl (in build file:/build/repo/)

113Execute excludeLibraryDependency: com.github.ghik:zerowaste_{scalaVersion} com.olegpy:better-monadic-for_3 org.polyvariant:better-tostring_{scalaVersion} org.wartremover:wartremover_{scalaVersion}

114[info] Reapplying settings...

115OpenCB::Failed to reapply settings in excludeLibraryDependency: Reference to undefined setting:

117 Global / allExcludeDependencies from Global / allExcludeDependencies (CommunityBuildPlugin.scala:331)

118 Did you mean allExcludeDependencies ?

119 , retry without global scopes

120[info] Reapplying settings...

121[info] set current project to dfhdl (in build file:/build/repo/)

122Execute removeScalacOptionsStartingWith: -P:wartremover

123[info] Reapplying settings...

124[info] set current project to dfhdl (in build file:/build/repo/)

125[success] Total time: 0 s, completed Dec 22, 2025, 7:00:13 PM

126Build config: {"projects":{"exclude":[],"overrides":{"dfhdl":{"tests":"compile-only"}}},"java":{"version":"17"},"sbt":{"commands":[],"options":[]},"mill":{"options":[]},"tests":"full","migrationVersions":[],"sourcePatches":[{"path":"build.sbt","pattern":"val compilerVersion = .*","replaceWith":"val compilerVersion = \"<SCALA_VERSION>\""}]}

127Parsed config: Success(ProjectBuildConfig(ProjectsConfig(List(),Map(dfhdl -> ProjectOverrides(Some(CompileOnly)))),Full,List()))

128Starting build...

129Projects: Set(plugin, compiler_ir, root, platforms, lib, internals, core, compiler_stages)

130Starting build for ProjectRef(file:/build/repo/,plugin) (dfhdl-plugin)... [0/8]

131OpenCB::Exclude Scala3 specific scalacOption `REQUIRE:-source:3.8` in Scala 2.12.20 module Global

132OpenCB::Filter out '-feature', matches setting pattern '^-?-feature'

133OpenCB::Filter out '-deprecation', matches setting pattern '^-?-deprecation'

134Compile scalacOptions: -unchecked, -language:strictEquality, -language:implicitConversions, -Wconf:msg=or backticked identifier `equals`:s, -Wconf:msg=not declared infix:s, -Wconf:msg=bad option '-Jdummy:s, -Wconf:msg=can be rewritten automatically under:s, -source:3.8

135[info] compiling 20 Scala sources to /build/repo/internals/target/scala-3.8.0-RC4/classes ...

138[info] done compiling

139[info] compiling 13 Scala sources to /build/repo/plugin/target/scala-3.8.0-RC4/classes ...

140[info] done compiling

141Starting build for ProjectRef(file:/build/repo/,platforms) (dfhdl-platforms)... [1/8]

142Compile scalacOptions: -unchecked, -language:strictEquality, -language:implicitConversions, -Wconf:msg=or backticked identifier `equals`:s, -Wconf:msg=not declared infix:s, -Wconf:msg=bad option '-Jdummy:s, -Xplugin:/build/repo/plugin/target/scala-3.8.0-RC4/dfhdl-plugin_3.8.0-RC4-0.16.0+0-b453bfec+20251222-1900-SNAPSHOT.jar, -Jdummy=1766426453453, -Wconf:msg=can be rewritten automatically under:s, -source:3.8

143[info] compiling 31 Scala sources to /build/repo/compiler/ir/target/scala-3.8.0-RC4/classes ...

144[info] done compiling

145[info] compiling 72 Scala sources to /build/repo/core/target/scala-3.8.0-RC4/classes ...

146[info] done compiling

147[info] compiling 65 Scala sources to /build/repo/compiler/stages/target/scala-3.8.0-RC4/classes ...

148[info] done compiling

149[info] compiling 53 Scala sources to /build/repo/lib/target/scala-3.8.0-RC4/classes ...

150[info] done compiling

151[info] compiling 42 Scala sources to /build/repo/platforms/target/scala-3.8.0-RC4/classes ...

152[info] done compiling

153[info] compiling 22 Scala sources to /build/repo/core/target/scala-3.8.0-RC4/test-classes ...

154[info] done compiling

155[info] compiling 9 Scala sources to /build/repo/platforms/target/scala-3.8.0-RC4/test-classes ...

165[info] done compiling

166PlatformSpec:

167 + Basys3 Seven Seg Display Connection Expected Error 0.229s

168Starting build for ProjectRef(file:/build/repo/,core) (dfhdl-core)... [2/8]

169Compile scalacOptions: -unchecked, -language:strictEquality, -language:implicitConversions, -Wconf:msg=or backticked identifier `equals`:s, -Wconf:msg=not declared infix:s, -Wconf:msg=bad option '-Jdummy:s, -Wconf:msg=can be rewritten automatically under:s, -source:3.8

170CoreSpec.DFStringSpec:

171 + String Operations 0.118s

172CoreSpec.DFDoubleSpec:

173 + Inlined width 0.019s

174 + Assignment 0.087s

175 + Arithmetic Operations 0.011s

176 + Comparison Operations 0.016s

177 + Type Conversion 0.006s

178CoreSpec.DFBoolOrBitSpec:

179 + Inlined width 0.004s

180 + Assignment 0.015s

181 + Logical Ops 0.031s

182CoreSpec.DFTupleSpec:

183 + Inlined width 0.002s

184 + Big Endian Packed Order 0.024s

185CoreSpec.DFEnumSpec:

186 + Type Construction 0.001s

187 + Inlined width 0.012s

188 + Enumeration Entries 0.009s

189 + Assignment 0.005s

190 + Comparison 0.001s

191 + Binary enum: conversions to Bit and Boolean 0.007s

192 + Binary enum: conversions from Bit and Boolean 0.008s

193 + Binary enum: logical not operation 0.018s

194 + Binary enum: comparison operations 0.006s

195CoreSpec.GlobalsSpec:

196 + Global errors 0.001s

197CoreSpec.DFUnitSpec:

198 + DFHDL Unit as bottom type 0.002s

199CoreSpec.DFStructSpec:

200 + Assignment 0.015s

201 + Showcase 0.115s

202 + ConstantErrors 0.001s

203 + Big Endian Packed Order 0.02s

204CoreSpec.DFOpaqueSpec:

205 + Inlined width 0.006s

206 + Connection error 0.002s

207 + Comparison 0.0s

208 + Assignment 0.001s

209CoreSpec.DFDecimalSpec:

210 + Type Construction 0.088s

211 + Inlined width 0.002s

212 + DFVal Conversion 0.057s

213 + Assignment 0.097s

214 + Comparison 0.035s

215 + Arithmetic 0.087s

216 + Int32 arithmetic 0.015s

217CoreSpec.ConnectAssignSpec:

218 + OPEN assignment is not allowed 0.104s

219 + NOTHING is not a constant 0.002s

220 + NOTHING constraints 0.05s

221CoreSpec.DFMatchSpec:

222 + No ret val 0.129s

223 + With ret val 0.053s

224 + Trivial tuple match skip 0.005s

225 + Different return widths error 0.008s

226CoreSpec.DFTypeSpec:

227 + Inlined width 0.003s

228 + codeString 0.006s

229 + value modifier limitations 0.011s

230CoreSpec.DFVectorSpec:

231 + Assignment 0.073s

232 + Big Endian Packed Order 0.093s

233 + Vector file initialization 0.078s

234CoreSpec.DFIfSpec:

235 + No ret val 0.066s

236 + With ret val 0.212s

237 + Different return widths error 0.007s

238CoreSpec.DFBitsSpec:

239 + Type Construction 0.002s

240 + Inlined width 0.0s

241 + DFVal Conversion 0.13s

242 + Assignment 0.038s

243 + DFVal Selection 0.009s

244 + Comparison 0.011s

245 + Bit reduction operations 0.021s

246 + Operations 0.006s

247Starting build for ProjectRef(file:/build/repo/,lib) (dfhdl)... [3/8]

248Compile scalacOptions: -unchecked, -language:strictEquality, -language:implicitConversions, -Wconf:msg=or backticked identifier `equals`:s, -Wconf:msg=not declared infix:s, -Wconf:msg=bad option '-Jdummy:s, -Xplugin:/build/repo/plugin/target/scala-3.8.0-RC4/dfhdl-plugin_3.8.0-RC4-0.16.0+0-b453bfec+20251222-1900-SNAPSHOT.jar, -Jdummy=1766426453453, -Wconf:msg=can be rewritten automatically under:s, -source:3.8

249[info] compiling 52 Scala sources to /build/repo/lib/target/scala-3.8.0-RC4/test-classes ...

250[info] done compiling

251Starting build for ProjectRef(file:/build/repo/,internals) (dfhdl-internals)... [4/8]

252Compile scalacOptions: -unchecked, -language:strictEquality, -language:implicitConversions, -Wconf:msg=or backticked identifier `equals`:s, -Wconf:msg=not declared infix:s, -Wconf:msg=bad option '-Jdummy:s, -Wconf:msg=can be rewritten automatically under:s, -source:3.8

253[info] compiling 3 Scala sources to /build/repo/internals/target/scala-3.8.0-RC4/test-classes ...

254[info] done compiling

255Starting build for ProjectRef(file:/build/repo/,compiler_ir) (dfhdl-compiler-ir)... [5/8]

256Compile scalacOptions: -unchecked, -language:strictEquality, -language:implicitConversions, -Wconf:msg=or backticked identifier `equals`:s, -Wconf:msg=not declared infix:s, -Wconf:msg=bad option '-Jdummy:s, -Wconf:msg=can be rewritten automatically under:s, -source:3.8

257Starting build for ProjectRef(file:/build/repo/,root) (dfhdl)... [6/8]

258Compile scalacOptions: -unchecked, -language:strictEquality, -language:implicitConversions, -Wconf:msg=or backticked identifier `equals`:s, -Wconf:msg=not declared infix:s, -Wconf:msg=bad option '-Jdummy:s, -Wconf:msg=can be rewritten automatically under:s, -source:3.8

259Starting build for ProjectRef(file:/build/repo/,compiler_stages) (dfhdl-compiler-stages)... [7/8]

260Compile scalacOptions: -unchecked, -language:strictEquality, -language:implicitConversions, -Wconf:msg=or backticked identifier `equals`:s, -Wconf:msg=not declared infix:s, -Wconf:msg=bad option '-Jdummy:s, -Wconf:msg=can be rewritten automatically under:s, -source:3.8

261[info] compiling 43 Scala sources to /build/repo/compiler/stages/target/scala-3.8.0-RC4/test-classes ...

262[info] done compiling

263StagesSpec.DropTimedRTWaitsSpec:

264 + wait with time duration 0.286s

265 + ED timed waits are not dropped 0.024s

266StagesSpec.DropDesignDefsSpec:

267 + Design def 0.068s

268 + Design def no return 0.018s

269StagesSpec.DropUnreferencedSpec:

270 + Drop unreferenced 0.008s

271 + Keep initialized unreferenced 0.012s

272StagesSpec.NamedSelectionSpec:

273 + Anonymous conditional expressions 0.292s

274 + Named selection multiple references 0.092s

275 + Ignore opaque type actual selection 0.04s

276 + Named selection with default parameter values 0.042s

277StagesSpec.SimplifyMatchSelSpec:

278 + UInt/SInt match selectors are converted to Bits match selectors 0.29s

279 + Design-parameterized UInt/SInt match selectors are converted to Bits match selectors 0.108s

280 + Bits global/local parameter selector is not dropped, but design parameter selection is dropped 0.084s

281StagesSpec.DropLocalDclsSpec:

282 + Nested local dcl move 0.028s

283 + Process also drops local dcls 0.034s

284 + Process keeps local dcls under VHDL 0.029s

285StagesSpec.ExplicitStateSpec:

286 + Basic explicit prev 0.285s

287 + If-else coverage 0.06s

288 + Global declaration, local usage, no prev 0.028s

289 + Partial assignment coverage 0.036s

290 + DFDecimal match pattern coverage 0.057s

291 + Bits match pattern coverage 0.103s

292 + Encoded match pattern coverage 0.046s

293 + ED domain remains unaffected 0.011s

294 + ALU regression test 0.022s

295StagesSpec.VHDLProcToVerilogSpec:

296 + Only clock 0.051s

297 + if reset else clock 0.059s

298 + internal clk/rst ports 0.089s

299StagesSpec.NameRegAliasesSpec:

300 + Basic reg alias + double application 0.076s

301 + State reg alias 0.032s

302 + Anonymous value reg aliases 0.037s

303 + Reg alias of mutating wire 0.023s

304 + Reg aliases with param init 0.037s

305 + Reg alias inside conditionals 0.03s

306 + Reg alias of a REG value has no versions 0.023s

307 + Reg alias inside domains 0.022s

308 + Alias is already named 0.028s

309StagesSpec.DropOpaquesSpec:

310 + Basic design with opaque types - drop all opaques 0.033s

311 + Opaque casting operations - drop all opaques 0.011s

312 + Complex hierarchy with opaque types - drop all opaques 0.043s

313 + Opaque types with complex operations - drop all opaques 0.02s

314 + Opaque types in vectors - drop all opaques 0.031s

315 + Opaque types in structs - drop all opaques 0.036s

316 + Opaque types with conditional logic - drop all opaques 0.022s

317 + Opaque types with function calls - drop all opaques 0.012s

318 + Opaque types with ports and connections - drop all opaques 0.019s

319 + Opaque types with initial values - drop all opaques 0.038s

320 + Opaque types with bit operations - drop all opaques 0.023s

321 + Opaque types with comparison operations - drop all opaques 0.022s

322 + Opaque types with nested structures - drop all opaques 0.032s

323 + Opaque types with vectors and indexing - drop all opaques 0.023s

324 + Opaque types with multiple assignments - drop all opaques 0.015s

325 + Opaque types with complex expressions - drop all opaques 0.016s

326 + Constant global vector of opaque types - drop all opaques 0.011s

327StagesSpec.BreakOpsSpec:

328 + Break vector concatenations 0.101s

329 + Break struct concatenations 0.032s

330StagesSpec.DropPhysicalValuesSpec:

331 + Basic physical value dropping 0.026s

332 + Basic physical value dropping with CLK_FREQ at combinational only 0.018s

333 + Basic physical value dropping with CLK_FREQ at combinational only-1 0.027s

334 + Physical value dropping with multiple domains at different frequencies 0.041s

335 + Physical value in wait statement is not dropped 0.009s

336 + Regression check when data caching caused issues 0.013s

337StagesSpec.ExplicitRomVarSpec:

338 + Basic constant vector ROM access 0.036s

339 + Multi-dimensional constant vector ROM access 0.025s

340 + Multiple ROM accesses in same design 0.031s

341 + ROM access in conditional block 0.022s

342 + ROM access in process block 0.027s

343 + No ROM creation for constant index access 0.008s

344 + No ROM creation for non-vector constants 0.014s

345 + No ROM creation for non-constant vectors 0.019s

346 + ROM creation only for supported backends 0.017s

347 + ROM creation with complex vector types 0.047s

348 + Global constant vector used in multiple internal designs 0.056s

349StagesSpec.UniqueNamesSpec:

350 + Unique names case-sensitive 0.02s

351 + Unique names case-insensitive 0.013s

352 + Unique named DFHDL types 0.047s

353StagesSpec.ExplicitNamedVarsSpec:

354 + Basic named variable 0.018s

355 + Named conditional expression 0.025s

356 + Nested named conditional expression 0.04s

357 + AES xtime example 0.019s

358StagesSpec.LocalToDesignParamsSpec:

359 + Local parameters used in IO are converted to design parameters 0.041s

360 + Local parameters used in nested designs are converted 0.03s

361 + Stage only runs for VHDL backends 0.012s

362 + Anonymous local parameters are not converted 0.006s

363 + Global parameters are not converted 0.017s

364 + Design parameters are not converted 0.021s

365 + Complex parameter expressions and different data types in IO 0.023s

366StagesSpec.ExplicitRegInitsSpec:

367 + Regs that require explicit init 0.024s

368 + Regs that have explicit init 0.028s

369 + Constant variable 0.011s

370StagesSpec.ViaConnectionSpec:

371 + Basic ID design 0.007s

372 + Basic ID design hierarchy 0.026s

373 + ID design hierarchy with unused output 0.017s

374 + Via-connection ID design hierarchy 0.032s

375 + Var intermediate connection design hierarchy 0.025s

376 + Via connection with partial selection 0.029s

377 + Via connection with partial selection 2 0.028s

378 + Hierarchical design with parameters 0.111s

379StagesSpec.ConnectMagnetsSpec:

380 + Basic design with magnet as in and out 0.011s

381 + Basic hierarchy with bottom-up and top-down magnet propagation 0.043s

382 + Basic hierarchy with bottom-up and THEN top-down magnet propagation 0.054s

383 + Basic hierarchy with variables as magnet sources 0.022s

384StagesSpec.AddClkRstSpec:

385 + Basic design clk and rst addition 0.02s

386 + Basic hierarchy, applied twice 0.04s

387 + Clk and rst already exist 0.026s

388 + No rst 0.022s

389 + No clk and rst 0.016s

390 + Add once for the same domain config between design and internal related domain 0.02s

391 + Add once for the same domain config between internal related domains 0.031s

392 + Explicit clk and rst are kept + constraints 0.036s

393 + Internal design generates clk and rst 0.023s

394 + Basic hierarchy with domains 0.03s

395 + Derive config with `.norst` 0.008s

396 + Top-level clk/rst are VARs 0.015s

397 + Top-level simulation clk/rst generated 0.029s

398 + Top-level simulation internal clk/rst declared 0.015s

399 + Top-level simulation clk only generated 0.032s

400 + Top-level simulation internal clk declared 0.023s

401StagesSpec.DropDomainsSpec:

402 + Mixed domain composition 0.042s

403 + Basic hierarchy with domains 0.046s

404StagesSpec.UniqueDesignsSpec:

405 + Unique designs 0.01s

406StagesSpec.ExplicitCondExprAssignSpec:

407 + Conditional expression assignment 0.018s

408 + Nested conditional expression assignment 0.056s

409 + AES xtime example 0.008s

410 + LRShiftFlat example 0.023s

411StagesSpec.ApplyInvertConstraintSpec:

412 + Basic input port inversion 0.009s

413 + Basic output port inversion 0.006s

414 + Basic registered initialized output port inversion 0.013s

415 + Both input and output ports inverted 0.011s

416 + Bits type inversion using bitwise NOT 0.014s

417 + Bits type inversion using bitwise NOT with mask 0.016s

418 + Multiple ports with mixed inversion 0.018s

419 + Double application has no effect 0.009s

420StagesSpec.DropOutportReadSpec:

421 + Basic outport read 0.012s

422StagesSpec.DropProcessAllSpec:

423 + Basic process 0.026s

424 + Conditional blocks in process 0.009s

425 + Conditional blocks in process + local variable 0.019s

426StagesSpec.AddMagnetsSpec:

427 + Basic design with magnet as in and out 0.014s

428 + Basic hierarchy with bottom-up and top-down magnet propagation 0.034s

429 + Basic hierarchy with bottom-up and THEN top-down magnet propagation 0.045s

430StagesSpec.DropBindsSpec:

431 + Drop binds 0.046s

432StagesSpec.DropStructsVecsSpec:

433 + Drop vector 0.04s

434 + Drop vector with parameters 0.056s

435 + Ignore block ram access vectors 0.053s

436 + Drop struct 0.017s

437 + Drop struct with parameters 0.041s

438 + Drop complex composition 0.029s

439 + Global constant vector 0.055s

440 + Inline anomaly 0.027s

441StagesSpec.DropRTProcessSpec:

442 + named FSM steps 0.047s

443 + unnamed FSM steps 0.039s

444 + process with no steps 0.007s

445StagesSpec.SimplifyRTOpsSpec:

446 + waitWhile to while loop transformation 0.018s

447 + ED domain is untouched 0.007s

448 + waitUntil to while loop and rising/falling edge transformation 0.015s

449 + multiple waitWhile transformations 0.009s

450 + wait with cycle duration 0.014s

451StagesSpec.DropDesignParamDepsSpec:

452 + Design parameter depending on another design parameter is inlined 0.021s

453 + Multiple design parameter dependencies are inlined 0.016s

454 + Stage only runs for VHDL'93 0.022s

455 + Stage does not run for Verilog backends 0.009s

456 + Nested design parameter dependencies are inlined 0.021s

457 + Complex parameter expressions are correctly evaluated 0.015s

458StagesSpec.PrintCodeStringSpec:

459 + Basic ID design 0.011s

460 + Basic ID design through companion constructor 0.012s

461 + Generic ID design 0.022s

462 + Basic ID design hierarchy 0.016s

463 + Generic ID design hierarchy 0.03s

464 + Via-connection ID design hierarchy 0.024s

465 + Design names affect named DFHDL types 0.013s

466 + RTDesign with class extension and parameters 0.017s

467 + DFInt32 parameter propagation 0.012s

468 + Basic EDDesign 0.014s

469 + Named anonymous multireference 0.012s

470 + Design def 0.035s

471 + Design def Unit return 0.025s

472 + Design def with toScalaValue effects 0.018s

473 + Named parameter should not be broken for IntP associative reductions 0.029s

474 + Domains 0.022s

475 + Basic hierarchy with domains 0.017s

476 + Docstrings 0.008s

477 + Blinker example 0.025s

478 + Unreachable anonymous global values 0.022s

479 + Unreachable local values 0.038s

480 + Cover case where same declaration domains are missing names 0.007s

481 + EDTrueDPR printing 0.046s

482 + Exported defs don't disrupt naming 0.004s

483 + Fixed precedence of connection RHS 0.006s

484 + Boolean selection operation 0.009s

485 + HighZ assignment 0.011s

486 + If printing with parametric width 0.014s

487 + Match printing with parametric width 0.021s

488 + RTDesign process printing 0.023s

489 + RTDesign process steps printing with onEntry and onExit 0.018s

490 + wait statements 0.01s

491 + for loop printing 0.047s

492 + for/while loop printing with COMB_LOOP 0.023s

493 + while loop printing 0.005s

494 + text out printing 0.03s

495 + out port of child design is not consuming state within the current design 0.005s

496 + dropping width parameter in patterns 0.03s

497 + constant vector regression 0.006s

498 + toggle enum printing 0.014s

499 + initialized port in duplicated design 0.011s

500 + qsys blackbox printing 0.02s

501 + qsys blackbox printing with extended ip class 0.012s

502StagesSpec.ConnectUnusedSpec:

503 + Connect unused ports to OPEN for internal design instances 0.017s

504 + Multiple internal design instances with unused ports 0.011s

505 + Top design unused ports are not affected 0.005s

506StagesSpec.PrintVHDLCodeSpec:

507 + Basic ID design 0.086s

508 + Basic hierarchy design 0.055s

509 + Basic hierarchy design with parameters 0.077s

510 + process block 0.035s

511 + literals 0.127s

512 + Blinker example 0.085s

513 + Opaque and vector local example 0.088s

514 + Vector local no conversion example 0.035s

515 + Opaque and vector global example 0.064s

516 + a single register with only init 0.027s

517 + Boolean selection operation 0.028s

518 + Empty design 0.015s

519 + HighZ assignment 0.022s

520 + Wildcards and don't cares 0.03s

521 + Wildcards and don't cares under vhdl.v93 0.057s

522 + Global parameters under vhdl.v93 0.082s

523 + wait statements 0.023s

524 + wait statements vhdl.v93 0.023s

525 + for loop printing 0.071s

526 + while loop printing 0.017s

527 + while loop printing vhdl.v93 0.012s

528 + text out printing 0.088s

529 + for loop with a register printing 0.054s

530 + pattern matching on anonymous value in vhdl.v93 0.026s

531 + toggle enum printing 0.022s

532 + qsys blackbox printing 0.026s

533StagesSpec.GlobalizePortVectorParams:

534 + Various vector params are kept 0.036s

535 + Various vector params are globalized, only ports are affected 0.06s

536 + Various vector params are kept under vhdl.v2008 0.044s

537 + Hierarchy parameter globalization 0.081s

538 + Hierarchy parameter globalization with the same parameter names 0.108s

539StagesSpec.ExplicitClkRstCfgSpec:

540 + Basic hierarchy, combinational 0.017s

541 + Basic hierarchy, combinational, always include clock and reset at top 0.013s

542 + Basic hierarchy, registered 0.016s

543 + Basic hierarchy with domains combinational, top domain = ED 0.019s

544 + Basic hierarchy with domains registered, top domain = ED 0.025s

545 + Basic hierarchy with domains combinational, top domain = RT 0.029s

546 + Basic hierarchy with domains registered, top domain = RT 0.024s

547 + Basic hierarchy with domains registered, top domain = RT, custom config 0.027s

548 + TrueDPR example 0.039s

549 + Regs with bubble init have no reset 0.011s

550 + Explicit clk/rst defined 0.008s

551 + RT domains get default configuration when owner is ED 0.024s

552 + Internal design generates clk and rst 0.03s

553 + Top-level clk/rst are VAR 0.012s

554StagesSpec.OrderMembersSpec:

555 + Simple order 0.006s

556 + Design blocks inside if 0.023s

557 + for loop inside if 0.022s

558StagesSpec.DropBAssignFromSeqProcSpec:

559 + moving sequential process blocking assignments 0.01s

560 + keeping a combinational process blocking assignments 0.005s

561StagesSpec.MatchToIfSpec:

562 + Basic pattern match remains the same 0.01s

563 + Basic pattern match with a guard 0.018s

564 + Basic pattern match with a guard, anonymous selector 0.015s

565 + Struct pattern match 0.042s

566 + Bits pattern match with wildcards 0.037s

567StagesSpec.ToEDSpec:

568 + Basic wires and reg 0.046s

569 + Rising clk, Async Reset 0.009s

570 + Falling clk, no Reset 0.011s

571 + Rising clk, Sync Reset & Active-low 0.018s

572 + Basic Hierarchy 0.038s

573 + Basic Bits Counter 0.032s

574 + Basic UInt Counter 0.026s

575 + Declaration with type operation 0.013s

576 + Inside conditional 0.029s

577 + REG declarations 0.031s

578 + DFMatch test case 1 0.013s

579 + DFMatch test case 2 0.019s

580 + If + param test case 0.02s

581 + Basic hierarchy with regs on outputs 0.044s

582 + Basic hierarchy with domains 0.066s

583 + RT domain with basic combinational if-else 0.018s

584 + a single register with only init 0.021s

585 + related domain uses external REG Dcls 0.025s

586 + register file example 0.049s

587 + left-right shift example 0.026s

588 + Basic hierarchy design with parameters 0.016s

589 + RT design with ED domain 0.013s

590 + Printing internal design port 0.016s

591 + For loop with a register 0.022s

592 + For loop with a register and combinational loop 0.031s

593 + match inside if 0.017s

594 + for loop inside if 0.014s

595 + regression check: a design with a single register 0.012s

596StagesSpec.PrintVerilogCodeSpec:

597 + Basic ID design 0.025s

598 + Basic hierarchy design 0.032s

599 + Basic hierarchy design with parameters 0.058s

600 + Basic hierarchy design with parameters verilog.v95 0.046s

601 + Global, design, and local parameters 0.018s

602 + process block 0.026s

603 + literals 0.071s

604 + Docstrings 0.012s

605 + Bits counter example 0.036s

606 + Various operations 0.039s

607 + UInt counter example 0.033s

608 + Blinker example 0.06s

609 + a single register with only init 0.02s

610 + Boolean selection operation 0.014s

611 + Empty design 0.004s

612 + HighZ assignment 0.009s

613 + Wildcards and don't cares 0.031s

614 + Wildcards and don't cares under verilog.v95 0.041s

615 + Global parameters under verilog.v95 0.055s

616 + wait statements 0.009s

617 + for loop printing 0.032s

618 + for loop printing verilog.v2001 0.058s

619 + while loop printing 0.008s

620 + text out printing 0.036s

621 + for loop with a register printing 0.02s

622 + vector init printing under verilog.v95 0.026s

623 + toggle enum printing 0.012s

624 + toggle enum printing under verilog.v2001 0.01s

625 + qsys blackbox printing 0.01s

626 + initialized output port register 0.008s

628************************

629Build summary:

630[{

631 "module": "dfhdl-plugin",

632 "compile": {"status": "ok", "tookMs": 20686, "warnings": 0, "errors": 0, "sourceVersion": "3.8"},

633 "doc": {"status": "skipped", "tookMs": 0, "files": 0, "totalSizeKb": 0},

634 "test-compile": {"status": "ok", "tookMs": 189, "warnings": 0, "errors": 0, "sourceVersion": "3.8"},

635 "test": {"status": "ok", "tookMs": 169, "passed": 0, "failed": 0, "ignored": 0, "skipped": 0, "total": 0, "byFramework": []},

636 "publish": {"status": "skipped", "tookMs": 0},

637 "metadata": {

638 "crossScalaVersions": []

639}

640},{

641 "module": "dfhdl-platforms",

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643 "doc": {"status": "skipped", "tookMs": 0, "files": 0, "totalSizeKb": 0},

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645 "test": {"status": "ok", "tookMs": 1021, "passed": 1, "failed": 0, "ignored": 0, "skipped": 0, "total": 1, "byFramework": [{"framework": "munit", "stats": {"passed": 1, "failed": 0, "ignored": 0, "skipped": 0, "total": 1}}]},

646 "publish": {"status": "skipped", "tookMs": 0},

647 "metadata": {

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653 "doc": {"status": "skipped", "tookMs": 0, "files": 0, "totalSizeKb": 0},

654 "test-compile": {"status": "ok", "tookMs": 204, "warnings": 0, "errors": 0, "sourceVersion": "3.8"},

655 "test": {"status": "ok", "tookMs": 1033, "passed": 61, "failed": 0, "ignored": 0, "skipped": 0, "total": 61, "byFramework": [{"framework": "munit", "stats": {"passed": 61, "failed": 0, "ignored": 0, "skipped": 0, "total": 61}}]},

656 "publish": {"status": "skipped", "tookMs": 0},

657 "metadata": {

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663 "doc": {"status": "skipped", "tookMs": 0, "files": 0, "totalSizeKb": 0},

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666 "publish": {"status": "skipped", "tookMs": 0},

667 "metadata": {

668 "crossScalaVersions": []

669}

670},{

671 "module": "dfhdl-internals",

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673 "doc": {"status": "skipped", "tookMs": 0, "files": 0, "totalSizeKb": 0},

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676 "publish": {"status": "skipped", "tookMs": 0},

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683 "doc": {"status": "skipped", "tookMs": 0, "files": 0, "totalSizeKb": 0},

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686 "publish": {"status": "skipped", "tookMs": 0},

687 "metadata": {

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703 "doc": {"status": "skipped", "tookMs": 0, "files": 0, "totalSizeKb": 0},

704 "test-compile": {"status": "ok", "tookMs": 61454, "warnings": 0, "errors": 0, "sourceVersion": "3.8"},

705 "test": {"status": "ok", "tookMs": 3406, "passed": 322, "failed": 0, "ignored": 0, "skipped": 0, "total": 322, "byFramework": [{"framework": "munit", "stats": {"passed": 322, "failed": 0, "ignored": 0, "skipped": 0, "total": 322}}]},

706 "publish": {"status": "skipped", "tookMs": 0},

707 "metadata": {

708 "crossScalaVersions": []

709}

710}]

711************************

712[success] Total time: 225 s (0:03:45.0), completed Dec 22, 2025, 7:03:59 PM

713[0JChecking patch project/plugins.sbt...

714Checking patch build.sbt...

715Applied patch project/plugins.sbt cleanly.

716Applied patch build.sbt cleanly.