Build Logs

1##################################

2Clonning https://github.com/dfianthdl/dfhdl.git into /build/repo using revision v0.16.0

3##################################

4Note: switching to 'b453bfec2949926e3a598e22a077b465b621fc59'.

6You are in 'detached HEAD' state. You can look around, make experimental

7changes and commit them, and you can discard any commits you make in this

8state without impacting any branches by switching back to a branch.

10If you want to create a new branch to retain commits you create, you may

11do so (now or later) by using -c with the switch command. Example:

13 git switch -c <new-branch-name>

15Or undo this operation with:

17 git switch -

19Turn off this advice by setting config variable advice.detachedHead to false

21----

22Preparing build for 3.8.0-RC5

23Scala binary version found: 3.8

24Implicitly using source version 3.8

25Scala binary version found: 3.8

26Implicitly using source version 3.8

27Would try to apply common scalacOption (best-effort, sbt/mill only):

28Append: ,REQUIRE:-source:3.8

29Remove: ,-deprecation,-feature,-Xfatal-warnings,-Werror,MATCH:.*-Wconf.*any:e

31Try apply source patch:

32Path: build.sbt

33Pattern: val compilerVersion = .*

34Replacement: val compilerVersion = "3.8.0-RC5"

35Starting compilation server

36Compiling project (Scala 3.7.3, JVM (17))

37Compiled project (Scala 3.7.3, JVM (17))

38Successfully applied pattern 'val compilerVersion = .*' in build.sbt

39----

40Starting build for 3.8.0-RC5

41Execute tests: true

42sbt project found:

43No prepare script found for project dfianthdl/dfhdl

44##################################

45Scala version: 3.8.0-RC5

46Targets: io.github.dfianthdl%dfhdl io.github.dfianthdl%dfhdl-compiler-ir io.github.dfianthdl%dfhdl-compiler-stages io.github.dfianthdl%dfhdl-core io.github.dfianthdl%dfhdl-internals io.github.dfianthdl%dfhdl-platforms

47Project projectConfig: {"projects":{"exclude":[],"overrides":{"dfhdl":{"tests":"compile-only"}}},"java":{"version":"17"},"sbt":{"commands":[],"options":[]},"mill":{"options":[]},"tests":"full","migrationVersions":[],"sourcePatches":[{"path":"build.sbt","pattern":"val compilerVersion = .*","replaceWith":"val compilerVersion = \"<SCALA_VERSION>\""}]}

48##################################

49Using extra scalacOptions: ,REQUIRE:-source:3.8

50Filtering out scalacOptions: ,-deprecation,-feature,-Xfatal-warnings,-Werror,MATCH:.*-Wconf.*any:e

51[sbt_options] declare -a sbt_options=()

52[process_args] java_version = '17'

53[copyRt] java9_rt = '/root/.sbt/1.0/java9-rt-ext-eclipse_adoptium_17_0_8/rt.jar'

54# Executing command line:

55java

56-Dfile.encoding=UTF-8

57-Dcommunitybuild.scala=3.8.0-RC5

58-Dcommunitybuild.project.dependencies.add=

59-Xmx7G

60-Xms4G

61-Xss8M

62-Dsbt.script=/root/.sdkman/candidates/sbt/current/bin/sbt

63-Dscala.ext.dirs=/root/.sbt/1.0/java9-rt-ext-eclipse_adoptium_17_0_8

64-jar

65/root/.sdkman/candidates/sbt/1.11.5/bin/sbt-launch.jar

66"setCrossScalaVersions 3.8.0-RC5"

67"++3.8.0-RC5 -v"

68"mapScalacOptions ",REQUIRE:-source:3.8,-Wconf:msg=can be rewritten automatically under:s" ",-deprecation,-feature,-Xfatal-warnings,-Werror,MATCH:.*-Wconf.*any:e""

69"set every credentials := Nil"

70"excludeLibraryDependency com.github.ghik:zerowaste_{scalaVersion} com.olegpy:better-monadic-for_3 org.polyvariant:better-tostring_{scalaVersion} org.wartremover:wartremover_{scalaVersion}"

71"removeScalacOptionsStartingWith -P:wartremover"

73moduleMappings

74"runBuild 3.8.0-RC5 """{"projects":{"exclude":[],"overrides":{"dfhdl":{"tests":"compile-only"}}},"java":{"version":"17"},"sbt":{"commands":[],"options":[]},"mill":{"options":[]},"tests":"full","migrationVersions":[],"sourcePatches":[{"path":"build.sbt","pattern":"val compilerVersion = .*","replaceWith":"val compilerVersion = \"<SCALA_VERSION>\""}]}""" io.github.dfianthdl%dfhdl io.github.dfianthdl%dfhdl-compiler-ir io.github.dfianthdl%dfhdl-compiler-stages io.github.dfianthdl%dfhdl-core io.github.dfianthdl%dfhdl-internals io.github.dfianthdl%dfhdl-platforms"

76[info] [launcher] getting org.scala-sbt sbt 1.11.7 (this may take some time)...

77[info] welcome to sbt 1.11.7 (Eclipse Adoptium Java 17.0.8)

78[info] loading settings for project repo-build from akka.sbt, plugins.sbt...

79[info] loading project definition from /build/repo/project

80[info] loading settings for project root from build.sbt...

81[info] set current project to dfhdl (in build file:/build/repo/)

82Execute setCrossScalaVersions: 3.8.0-RC5

83OpenCB::Changing crossVersion 3.8.0-RC5 -> 3.8.0-RC5 in core/crossScalaVersions

84OpenCB::Changing crossVersion 3.8.0-RC5 -> 3.8.0-RC5 in compiler_ir/crossScalaVersions

85OpenCB::Changing crossVersion 3.8.0-RC5 -> 3.8.0-RC5 in plugin/crossScalaVersions

86OpenCB::Changing crossVersion 3.8.0-RC5 -> 3.8.0-RC5 in internals/crossScalaVersions

87OpenCB::Changing crossVersion 3.8.0-RC5 -> 3.8.0-RC5 in platforms/crossScalaVersions

88OpenCB::Changing crossVersion 3.8.0-RC5 -> 3.8.0-RC5 in compiler_stages/crossScalaVersions

89OpenCB::Changing crossVersion 3.8.0-RC5 -> 3.8.0-RC5 in root/crossScalaVersions

90OpenCB::Changing crossVersion 3.8.0-RC5 -> 3.8.0-RC5 in lib/crossScalaVersions

91[info] set current project to dfhdl (in build file:/build/repo/)

92[info] Setting Scala version to 3.8.0-RC5 on 8 projects.

93[info] Switching Scala version on:

94[info] plugin (3.8.0-RC5)

95[info] compiler_ir (3.8.0-RC5)

96[info] * root (3.8.0-RC5)

97[info] platforms (3.8.0-RC5)

98[info] lib (3.8.0-RC5)

99[info] internals (3.8.0-RC5)

100[info] core (3.8.0-RC5)

101[info] compiler_stages (3.8.0-RC5)

102[info] Excluding projects:

103[info] Reapplying settings...

104[info] set current project to dfhdl (in build file:/build/repo/)

105Execute mapScalacOptions: ,REQUIRE:-source:3.8,-Wconf:msg=can be rewritten automatically under:s ,-deprecation,-feature,-Xfatal-warnings,-Werror,MATCH:.*-Wconf.*any:e

106[info] Reapplying settings...

107[info] set current project to dfhdl (in build file:/build/repo/)

108[info] Defining Global / credentials, compiler_ir / credentials and 6 others.

109[info] The new values will be used by Global / pgpSelectPassphrase, Global / pgpSigningKey and 39 others.

110[info] Run `last` for details.

111[info] Reapplying settings...

112[info] set current project to dfhdl (in build file:/build/repo/)

113Execute excludeLibraryDependency: com.github.ghik:zerowaste_{scalaVersion} com.olegpy:better-monadic-for_3 org.polyvariant:better-tostring_{scalaVersion} org.wartremover:wartremover_{scalaVersion}

114[info] Reapplying settings...

115OpenCB::Failed to reapply settings in excludeLibraryDependency: Reference to undefined setting:

117 Global / allExcludeDependencies from Global / allExcludeDependencies (CommunityBuildPlugin.scala:331)

118 Did you mean allExcludeDependencies ?

119 , retry without global scopes

120[info] Reapplying settings...

121[info] set current project to dfhdl (in build file:/build/repo/)

122Execute removeScalacOptionsStartingWith: -P:wartremover

123[info] Reapplying settings...

124[info] set current project to dfhdl (in build file:/build/repo/)

125[success] Total time: 0 s, completed Dec 31, 2025, 9:37:33 PM

126Build config: {"projects":{"exclude":[],"overrides":{"dfhdl":{"tests":"compile-only"}}},"java":{"version":"17"},"sbt":{"commands":[],"options":[]},"mill":{"options":[]},"tests":"full","migrationVersions":[],"sourcePatches":[{"path":"build.sbt","pattern":"val compilerVersion = .*","replaceWith":"val compilerVersion = \"<SCALA_VERSION>\""}]}

127Parsed config: Success(ProjectBuildConfig(ProjectsConfig(List(),Map(dfhdl -> ProjectOverrides(Some(CompileOnly)))),Full,List()))

128Starting build...

129Projects: Set(plugin, compiler_ir, root, platforms, lib, internals, core, compiler_stages)

130Starting build for ProjectRef(file:/build/repo/,plugin) (dfhdl-plugin)... [0/8]

131OpenCB::Exclude Scala3 specific scalacOption `REQUIRE:-source:3.8` in Scala 2.12.20 module Global

132OpenCB::Filter out '-feature', matches setting pattern '^-?-feature'

133OpenCB::Filter out '-deprecation', matches setting pattern '^-?-deprecation'

134Compile scalacOptions: -unchecked, -language:strictEquality, -language:implicitConversions, -Wconf:msg=or backticked identifier `equals`:s, -Wconf:msg=not declared infix:s, -Wconf:msg=bad option '-Jdummy:s, -Wconf:msg=can be rewritten automatically under:s, -source:3.8

135[info] compiling 20 Scala sources to /build/repo/internals/target/scala-3.8.0-RC5/classes ...

138[info] done compiling

139[info] compiling 13 Scala sources to /build/repo/plugin/target/scala-3.8.0-RC5/classes ...

140[info] done compiling

141Starting build for ProjectRef(file:/build/repo/,platforms) (dfhdl-platforms)... [1/8]

142Compile scalacOptions: -unchecked, -language:strictEquality, -language:implicitConversions, -Wconf:msg=or backticked identifier `equals`:s, -Wconf:msg=not declared infix:s, -Wconf:msg=bad option '-Jdummy:s, -Xplugin:/build/repo/plugin/target/scala-3.8.0-RC5/dfhdl-plugin_3.8.0-RC5-0.16.0+0-b453bfec+20251231-2137-SNAPSHOT.jar, -Jdummy=1767213474735, -Wconf:msg=can be rewritten automatically under:s, -source:3.8

143[info] compiling 31 Scala sources to /build/repo/compiler/ir/target/scala-3.8.0-RC5/classes ...

144[info] done compiling

145[info] compiling 72 Scala sources to /build/repo/core/target/scala-3.8.0-RC5/classes ...

146[info] done compiling

147[info] compiling 65 Scala sources to /build/repo/compiler/stages/target/scala-3.8.0-RC5/classes ...

148[info] done compiling

149[info] compiling 53 Scala sources to /build/repo/lib/target/scala-3.8.0-RC5/classes ...

150[info] done compiling

151[info] compiling 42 Scala sources to /build/repo/platforms/target/scala-3.8.0-RC5/classes ...

152[info] done compiling

153[info] compiling 22 Scala sources to /build/repo/core/target/scala-3.8.0-RC5/test-classes ...

154[info] done compiling

155[info] compiling 9 Scala sources to /build/repo/platforms/target/scala-3.8.0-RC5/test-classes ...

165[info] done compiling

166PlatformSpec:

167 + Basys3 Seven Seg Display Connection Expected Error 0.287s

168Starting build for ProjectRef(file:/build/repo/,core) (dfhdl-core)... [2/8]

169Compile scalacOptions: -unchecked, -language:strictEquality, -language:implicitConversions, -Wconf:msg=or backticked identifier `equals`:s, -Wconf:msg=not declared infix:s, -Wconf:msg=bad option '-Jdummy:s, -Wconf:msg=can be rewritten automatically under:s, -source:3.8

170CoreSpec.DFStringSpec:

171 + String Operations 0.137s

172CoreSpec.DFUnitSpec:

173 + DFHDL Unit as bottom type 0.003s

174CoreSpec.GlobalsSpec:

175 + Global errors 0.001s

176CoreSpec.DFStructSpec:

177 + Assignment 0.009s

178 + Showcase 0.063s

179 + ConstantErrors 0.001s

180 + Big Endian Packed Order 0.018s

181CoreSpec.DFOpaqueSpec:

182 + Inlined width 0.009s

183 + Connection error 0.002s

184 + Comparison 0.003s

185 + Assignment 0.001s

186CoreSpec.DFMatchSpec:

187 + No ret val 0.198s

188 + With ret val 0.034s

189 + Trivial tuple match skip 0.003s

190 + Different return widths error 0.008s

191CoreSpec.DFTypeSpec:

192 + Inlined width 0.006s

193 + codeString 0.01s

194 + value modifier limitations 0.005s

195CoreSpec.DFBoolOrBitSpec:

196 + Inlined width 0.001s

197 + Assignment 0.013s

198 + Logical Ops 0.025s

199CoreSpec.DFDoubleSpec:

200 + Inlined width 0.006s

201 + Assignment 0.007s

202 + Arithmetic Operations 0.011s

203 + Comparison Operations 0.015s

204 + Type Conversion 0.002s

205CoreSpec.DFIfSpec:

206 + No ret val 0.201s

207 + With ret val 0.167s

208 + Different return widths error 0.005s

209CoreSpec.ConnectAssignSpec:

210 + OPEN assignment is not allowed 0.161s

211 + NOTHING is not a constant 0.002s

212 + NOTHING constraints 0.049s

213CoreSpec.DFEnumSpec:

214 + Type Construction 0.001s

215 + Inlined width 0.001s

216 + Enumeration Entries 0.011s

217 + Assignment 0.01s

218 + Comparison 0.005s

219 + Binary enum: conversions to Bit and Boolean 0.007s

220 + Binary enum: conversions from Bit and Boolean 0.008s

221 + Binary enum: logical not operation 0.004s

222 + Binary enum: comparison operations 0.012s

223CoreSpec.DFBitsSpec:

224 + Type Construction 0.002s

225 + Inlined width 0.0s

226 + DFVal Conversion 0.123s

227 + Assignment 0.048s

228 + DFVal Selection 0.022s

229 + Comparison 0.009s

230 + Bit reduction operations 0.017s

231 + Operations 0.019s

232CoreSpec.DFTupleSpec:

233 + Inlined width 0.002s

234 + Big Endian Packed Order 0.01s

235CoreSpec.DFVectorSpec:

236 + Assignment 0.065s

237 + Big Endian Packed Order 0.03s

238 + Vector file initialization 0.055s

239CoreSpec.DFDecimalSpec:

240 + Type Construction 0.015s

241 + Inlined width 0.001s

242 + DFVal Conversion 0.017s

243 + Assignment 0.071s

244 + Comparison 0.019s

245 + Arithmetic 0.042s

246 + Int32 arithmetic 0.008s

247Starting build for ProjectRef(file:/build/repo/,lib) (dfhdl)... [3/8]

248Compile scalacOptions: -unchecked, -language:strictEquality, -language:implicitConversions, -Wconf:msg=or backticked identifier `equals`:s, -Wconf:msg=not declared infix:s, -Wconf:msg=bad option '-Jdummy:s, -Xplugin:/build/repo/plugin/target/scala-3.8.0-RC5/dfhdl-plugin_3.8.0-RC5-0.16.0+0-b453bfec+20251231-2137-SNAPSHOT.jar, -Jdummy=1767213474735, -Wconf:msg=can be rewritten automatically under:s, -source:3.8

249[info] compiling 52 Scala sources to /build/repo/lib/target/scala-3.8.0-RC5/test-classes ...

250[info] done compiling

251Starting build for ProjectRef(file:/build/repo/,internals) (dfhdl-internals)... [4/8]

252Compile scalacOptions: -unchecked, -language:strictEquality, -language:implicitConversions, -Wconf:msg=or backticked identifier `equals`:s, -Wconf:msg=not declared infix:s, -Wconf:msg=bad option '-Jdummy:s, -Wconf:msg=can be rewritten automatically under:s, -source:3.8

253[info] compiling 3 Scala sources to /build/repo/internals/target/scala-3.8.0-RC5/test-classes ...

254[info] done compiling

255Starting build for ProjectRef(file:/build/repo/,compiler_ir) (dfhdl-compiler-ir)... [5/8]

256Compile scalacOptions: -unchecked, -language:strictEquality, -language:implicitConversions, -Wconf:msg=or backticked identifier `equals`:s, -Wconf:msg=not declared infix:s, -Wconf:msg=bad option '-Jdummy:s, -Wconf:msg=can be rewritten automatically under:s, -source:3.8

257Starting build for ProjectRef(file:/build/repo/,root) (dfhdl)... [6/8]

258Compile scalacOptions: -unchecked, -language:strictEquality, -language:implicitConversions, -Wconf:msg=or backticked identifier `equals`:s, -Wconf:msg=not declared infix:s, -Wconf:msg=bad option '-Jdummy:s, -Wconf:msg=can be rewritten automatically under:s, -source:3.8

259Starting build for ProjectRef(file:/build/repo/,compiler_stages) (dfhdl-compiler-stages)... [7/8]

260Compile scalacOptions: -unchecked, -language:strictEquality, -language:implicitConversions, -Wconf:msg=or backticked identifier `equals`:s, -Wconf:msg=not declared infix:s, -Wconf:msg=bad option '-Jdummy:s, -Wconf:msg=can be rewritten automatically under:s, -source:3.8

261[info] compiling 43 Scala sources to /build/repo/compiler/stages/target/scala-3.8.0-RC5/test-classes ...

262[info] done compiling

263StagesSpec.LocalToDesignParamsSpec:

264 + Local parameters used in IO are converted to design parameters 0.259s

265 + Local parameters used in nested designs are converted 0.04s

266 + Stage only runs for VHDL backends 0.015s

267 + Anonymous local parameters are not converted 0.009s

268 + Global parameters are not converted 0.017s

269 + Design parameters are not converted 0.01s

270 + Complex parameter expressions and different data types in IO 0.051s

271StagesSpec.ExplicitNamedVarsSpec:

272 + Basic named variable 0.259s

273 + Named conditional expression 0.079s

274 + Nested named conditional expression 0.092s

275 + AES xtime example 0.097s

276StagesSpec.GlobalizePortVectorParams:

277 + Various vector params are kept 0.261s

278 + Various vector params are globalized, only ports are affected 0.108s

279 + Various vector params are kept under vhdl.v2008 0.049s

280 + Hierarchy parameter globalization 0.148s

281 + Hierarchy parameter globalization with the same parameter names 0.158s

282StagesSpec.DropOpaquesSpec:

283 + Basic design with opaque types - drop all opaques 0.041s

284 + Opaque casting operations - drop all opaques 0.019s

285 + Complex hierarchy with opaque types - drop all opaques 0.034s

286 + Opaque types with complex operations - drop all opaques 0.03s

287 + Opaque types in vectors - drop all opaques 0.026s

288 + Opaque types in structs - drop all opaques 0.046s

289 + Opaque types with conditional logic - drop all opaques 0.021s

290 + Opaque types with function calls - drop all opaques 0.018s

291 + Opaque types with ports and connections - drop all opaques 0.024s

292 + Opaque types with initial values - drop all opaques 0.039s

293 + Opaque types with bit operations - drop all opaques 0.028s

294 + Opaque types with comparison operations - drop all opaques 0.033s

295 + Opaque types with nested structures - drop all opaques 0.027s

296 + Opaque types with vectors and indexing - drop all opaques 0.022s

297 + Opaque types with multiple assignments - drop all opaques 0.024s

298 + Opaque types with complex expressions - drop all opaques 0.035s

299 + Constant global vector of opaque types - drop all opaques 0.014s

300StagesSpec.ExplicitRomVarSpec:

301 + Basic constant vector ROM access 0.029s

302 + Multi-dimensional constant vector ROM access 0.052s

303 + Multiple ROM accesses in same design 0.041s

304 + ROM access in conditional block 0.025s

305 + ROM access in process block 0.022s

306 + No ROM creation for constant index access 0.016s

307 + No ROM creation for non-vector constants 0.012s

308 + No ROM creation for non-constant vectors 0.016s

309 + ROM creation only for supported backends 0.014s

310 + ROM creation with complex vector types 0.041s

311 + Global constant vector used in multiple internal designs 0.035s

312StagesSpec.DropDomainsSpec:

313 + Mixed domain composition 0.032s

314 + Basic hierarchy with domains 0.055s

315StagesSpec.SimplifyMatchSelSpec:

316 + UInt/SInt match selectors are converted to Bits match selectors 0.042s

317 + Design-parameterized UInt/SInt match selectors are converted to Bits match selectors 0.034s

318 + Bits global/local parameter selector is not dropped, but design parameter selection is dropped 0.042s

319StagesSpec.NamedSelectionSpec:

320 + Anonymous conditional expressions 0.024s

321 + Named selection multiple references 0.034s

322 + Ignore opaque type actual selection 0.01s

323 + Named selection with default parameter values 0.015s

324StagesSpec.DropRTProcessSpec:

325 + named FSM steps 0.045s

326 + unnamed FSM steps 0.039s

327 + process with no steps 0.007s

328StagesSpec.BreakOpsSpec:

329 + Break vector concatenations 0.072s

330 + Break struct concatenations 0.048s

331StagesSpec.PrintCodeStringSpec:

332 + Basic ID design 0.026s

333 + Basic ID design through companion constructor 0.011s

334 + Generic ID design 0.037s

335 + Basic ID design hierarchy 0.029s

336 + Generic ID design hierarchy 0.036s

337 + Via-connection ID design hierarchy 0.027s

338 + Design names affect named DFHDL types 0.014s

339 + RTDesign with class extension and parameters 0.06s

340 + DFInt32 parameter propagation 0.022s

341 + Basic EDDesign 0.031s

342 + Named anonymous multireference 0.031s

343 + Design def 0.079s

344 + Design def Unit return 0.009s

345 + Design def with toScalaValue effects 0.031s

346 + Named parameter should not be broken for IntP associative reductions 0.05s

347 + Domains 0.044s

348 + Basic hierarchy with domains 0.03s

349 + Docstrings 0.011s

350 + Blinker example 0.054s

351 + Unreachable anonymous global values 0.018s

352 + Unreachable local values 0.035s

353 + Cover case where same declaration domains are missing names 0.017s

354 + EDTrueDPR printing 0.044s

355 + Exported defs don't disrupt naming 0.011s

356 + Fixed precedence of connection RHS 0.012s

357 + Boolean selection operation 0.019s

358 + HighZ assignment 0.011s

359 + If printing with parametric width 0.021s

360 + Match printing with parametric width 0.019s

361 + RTDesign process printing 0.026s

362 + RTDesign process steps printing with onEntry and onExit 0.03s

363 + wait statements 0.018s

364 + for loop printing 0.045s

365 + for/while loop printing with COMB_LOOP 0.03s

366 + while loop printing 0.007s

367 + text out printing 0.063s

368 + out port of child design is not consuming state within the current design 0.005s

369 + dropping width parameter in patterns 0.017s

370 + constant vector regression 0.01s

371 + toggle enum printing 0.019s

372 + initialized port in duplicated design 0.015s

373 + qsys blackbox printing 0.027s

374 + qsys blackbox printing with extended ip class 0.02s

375StagesSpec.DropProcessAllSpec:

376 + Basic process 0.012s

377 + Conditional blocks in process 0.024s

378 + Conditional blocks in process + local variable 0.017s

379StagesSpec.DropBindsSpec:

380 + Drop binds 0.054s

381StagesSpec.DropLocalDclsSpec:

382 + Nested local dcl move 0.036s

383 + Process also drops local dcls 0.026s

384 + Process keeps local dcls under VHDL 0.026s

385StagesSpec.DropUnreferencedSpec:

386 + Drop unreferenced 0.007s

387 + Keep initialized unreferenced 0.015s

388StagesSpec.UniqueDesignsSpec:

389 + Unique designs 0.016s

390StagesSpec.DropDesignParamDepsSpec:

391 + Design parameter depending on another design parameter is inlined 0.024s

392 + Multiple design parameter dependencies are inlined 0.024s

393 + Stage only runs for VHDL'93 0.016s

394 + Stage does not run for Verilog backends 0.013s

395 + Nested design parameter dependencies are inlined 0.043s

396 + Complex parameter expressions are correctly evaluated 0.018s

397StagesSpec.PrintVHDLCodeSpec:

398 + Basic ID design 0.275s

399 + Basic hierarchy design 0.065s

400 + Basic hierarchy design with parameters 0.133s

401 + process block 0.071s

402 + literals 0.246s

403 + Blinker example 0.118s

404 + Opaque and vector local example 0.092s

405 + Vector local no conversion example 0.026s

406 + Opaque and vector global example 0.08s

407 + a single register with only init 0.027s

408 + Boolean selection operation 0.036s

409 + Empty design 0.013s

410 + HighZ assignment 0.025s

411 + Wildcards and don't cares 0.048s

412 + Wildcards and don't cares under vhdl.v93 0.074s

413 + Global parameters under vhdl.v93 0.079s

414 + wait statements 0.012s

415 + wait statements vhdl.v93 0.013s

416 + for loop printing 0.056s

417 + while loop printing 0.023s

418 + while loop printing vhdl.v93 0.024s

419 + text out printing 0.105s

420 + for loop with a register printing 0.067s

421 + pattern matching on anonymous value in vhdl.v93 0.029s

422 + toggle enum printing 0.046s

423 + qsys blackbox printing 0.037s

424StagesSpec.DropDesignDefsSpec:

425 + Design def 0.014s

426 + Design def no return 0.006s

427StagesSpec.ExplicitRegInitsSpec:

428 + Regs that require explicit init 0.012s

429 + Regs that have explicit init 0.027s

430 + Constant variable 0.015s

431StagesSpec.OrderMembersSpec:

432 + Simple order 0.008s

433 + Design blocks inside if 0.021s

434 + for loop inside if 0.028s

435StagesSpec.MatchToIfSpec:

436 + Basic pattern match remains the same 0.017s

437 + Basic pattern match with a guard 0.027s

438 + Basic pattern match with a guard, anonymous selector 0.023s

439 + Struct pattern match 0.028s

440 + Bits pattern match with wildcards 0.016s

441StagesSpec.ConnectUnusedSpec:

442 + Connect unused ports to OPEN for internal design instances 0.019s

443 + Multiple internal design instances with unused ports 0.027s

444 + Top design unused ports are not affected 0.017s

445StagesSpec.ViaConnectionSpec:

446 + Basic ID design 0.008s

447 + Basic ID design hierarchy 0.034s

448 + ID design hierarchy with unused output 0.015s

449 + Via-connection ID design hierarchy 0.021s

450 + Var intermediate connection design hierarchy 0.03s

451 + Via connection with partial selection 0.039s

452 + Via connection with partial selection 2 0.02s

453 + Hierarchical design with parameters 0.104s

454StagesSpec.VHDLProcToVerilogSpec:

455 + Only clock 0.019s

456 + if reset else clock 0.046s

457 + internal clk/rst ports 0.043s

458StagesSpec.DropBAssignFromSeqProcSpec:

459 + moving sequential process blocking assignments 0.014s

460 + keeping a combinational process blocking assignments 0.011s

461StagesSpec.DropStructsVecsSpec:

462 + Drop vector 0.015s

463 + Drop vector with parameters 0.058s

464 + Ignore block ram access vectors 0.056s

465 + Drop struct 0.022s

466 + Drop struct with parameters 0.043s

467 + Drop complex composition 0.032s

468 + Global constant vector 0.062s

469 + Inline anomaly 0.032s

470StagesSpec.AddMagnetsSpec:

471 + Basic design with magnet as in and out 0.013s

472 + Basic hierarchy with bottom-up and top-down magnet propagation 0.023s

473 + Basic hierarchy with bottom-up and THEN top-down magnet propagation 0.031s

474StagesSpec.DropOutportReadSpec:

475 + Basic outport read 0.007s

476StagesSpec.PrintVerilogCodeSpec:

477 + Basic ID design 0.039s

478 + Basic hierarchy design 0.035s

479 + Basic hierarchy design with parameters 0.056s

480 + Basic hierarchy design with parameters verilog.v95 0.07s

481 + Global, design, and local parameters 0.02s

482 + process block 0.045s

483 + literals 0.081s

484 + Docstrings 0.015s

485 + Bits counter example 0.042s

486 + Various operations 0.054s

487 + UInt counter example 0.032s

488 + Blinker example 0.055s

489 + a single register with only init 0.016s

490 + Boolean selection operation 0.038s

491 + Empty design 0.008s

492 + HighZ assignment 0.009s

493 + Wildcards and don't cares 0.03s

494 + Wildcards and don't cares under verilog.v95 0.039s

495 + Global parameters under verilog.v95 0.096s

496 + wait statements 0.015s

497 + for loop printing 0.08s

498 + for loop printing verilog.v2001 0.1s

499 + while loop printing 0.01s

500 + text out printing 0.108s

501 + for loop with a register printing 0.052s

502 + vector init printing under verilog.v95 0.048s

503 + toggle enum printing 0.021s

504 + toggle enum printing under verilog.v2001 0.023s

505 + qsys blackbox printing 0.028s

506 + initialized output port register 0.017s

507StagesSpec.ExplicitStateSpec:

508 + Basic explicit prev 0.018s

509 + If-else coverage 0.024s

510 + Global declaration, local usage, no prev 0.012s

511 + Partial assignment coverage 0.007s

512 + DFDecimal match pattern coverage 0.033s

513 + Bits match pattern coverage 0.06s

514 + Encoded match pattern coverage 0.021s

515 + ED domain remains unaffected 0.008s

516 + ALU regression test 0.011s

517StagesSpec.ExplicitClkRstCfgSpec:

518 + Basic hierarchy, combinational 0.015s

519 + Basic hierarchy, combinational, always include clock and reset at top 0.011s

520 + Basic hierarchy, registered 0.019s

521 + Basic hierarchy with domains combinational, top domain = ED 0.025s

522 + Basic hierarchy with domains registered, top domain = ED 0.027s

523 + Basic hierarchy with domains combinational, top domain = RT 0.021s

524 + Basic hierarchy with domains registered, top domain = RT 0.014s

525 + Basic hierarchy with domains registered, top domain = RT, custom config 0.028s

526 + TrueDPR example 0.043s

527 + Regs with bubble init have no reset 0.008s

528 + Explicit clk/rst defined 0.007s

529 + RT domains get default configuration when owner is ED 0.032s

530 + Internal design generates clk and rst 0.028s

531 + Top-level clk/rst are VAR 0.019s

532StagesSpec.SimplifyRTOpsSpec:

533 + waitWhile to while loop transformation 0.017s

534 + ED domain is untouched 0.01s

535 + waitUntil to while loop and rising/falling edge transformation 0.026s

536 + multiple waitWhile transformations 0.011s

537 + wait with cycle duration 0.025s

538StagesSpec.DropPhysicalValuesSpec:

539 + Basic physical value dropping 0.018s

540 + Basic physical value dropping with CLK_FREQ at combinational only 0.014s

541 + Basic physical value dropping with CLK_FREQ at combinational only-1 0.014s

542 + Physical value dropping with multiple domains at different frequencies 0.029s

543 + Physical value in wait statement is not dropped 0.014s

544 + Regression check when data caching caused issues 0.007s

545StagesSpec.AddClkRstSpec:

546 + Basic design clk and rst addition 0.015s

547 + Basic hierarchy, applied twice 0.021s

548 + Clk and rst already exist 0.037s

549 + No rst 0.011s

550 + No clk and rst 0.013s

551 + Add once for the same domain config between design and internal related domain 0.013s

552 + Add once for the same domain config between internal related domains 0.02s

553 + Explicit clk and rst are kept + constraints 0.037s

554 + Internal design generates clk and rst 0.032s

555 + Basic hierarchy with domains 0.031s

556 + Derive config with `.norst` 0.014s

557 + Top-level clk/rst are VARs 0.017s

558 + Top-level simulation clk/rst generated 0.03s

559 + Top-level simulation internal clk/rst declared 0.02s

560 + Top-level simulation clk only generated 0.028s

561 + Top-level simulation internal clk declared 0.015s

562StagesSpec.DropTimedRTWaitsSpec:

563 + wait with time duration 0.009s

564 + ED timed waits are not dropped 0.009s

565StagesSpec.UniqueNamesSpec:

566 + Unique names case-sensitive 0.023s

567 + Unique names case-insensitive 0.008s

568 + Unique named DFHDL types 0.024s

569StagesSpec.ApplyInvertConstraintSpec:

570 + Basic input port inversion 0.007s

571 + Basic output port inversion 0.009s

572 + Basic registered initialized output port inversion 0.015s

573 + Both input and output ports inverted 0.009s

574 + Bits type inversion using bitwise NOT 0.015s

575 + Bits type inversion using bitwise NOT with mask 0.013s

576 + Multiple ports with mixed inversion 0.022s

577 + Double application has no effect 0.013s

578StagesSpec.ExplicitCondExprAssignSpec:

579 + Conditional expression assignment 0.02s

580 + Nested conditional expression assignment 0.029s

581 + AES xtime example 0.006s

582 + LRShiftFlat example 0.021s

583StagesSpec.ConnectMagnetsSpec:

584 + Basic design with magnet as in and out 0.013s

585 + Basic hierarchy with bottom-up and top-down magnet propagation 0.036s

586 + Basic hierarchy with bottom-up and THEN top-down magnet propagation 0.054s

587 + Basic hierarchy with variables as magnet sources 0.015s

588StagesSpec.NameRegAliasesSpec:

589 + Basic reg alias + double application 0.014s

590 + State reg alias 0.008s

591 + Anonymous value reg aliases 0.012s

592 + Reg alias of mutating wire 0.013s

593 + Reg aliases with param init 0.025s

594 + Reg alias inside conditionals 0.016s

595 + Reg alias of a REG value has no versions 0.01s

596 + Reg alias inside domains 0.022s

597 + Alias is already named 0.016s

598StagesSpec.ToEDSpec:

599 + Basic wires and reg 0.044s

600 + Rising clk, Async Reset 0.016s

601 + Falling clk, no Reset 0.011s

602 + Rising clk, Sync Reset & Active-low 0.013s

603 + Basic Hierarchy 0.042s

604 + Basic Bits Counter 0.032s

605 + Basic UInt Counter 0.033s

606 + Declaration with type operation 0.016s

607 + Inside conditional 0.029s

608 + REG declarations 0.04s

609 + DFMatch test case 1 0.018s

610 + DFMatch test case 2 0.014s

611 + If + param test case 0.018s

612 + Basic hierarchy with regs on outputs 0.037s

613 + Basic hierarchy with domains 0.05s

614 + RT domain with basic combinational if-else 0.02s

615 + a single register with only init 0.013s

616 + related domain uses external REG Dcls 0.021s

617 + register file example 0.057s

618 + left-right shift example 0.05s

619 + Basic hierarchy design with parameters 0.029s

620 + RT design with ED domain 0.016s

621 + Printing internal design port 0.037s

622 + For loop with a register 0.052s

623 + For loop with a register and combinational loop 0.038s

624 + match inside if 0.019s

625 + for loop inside if 0.016s

626 + regression check: a design with a single register 0.012s

628************************

629Build summary:

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711************************

712[success] Total time: 201 s (0:03:21.0), completed Dec 31, 2025, 9:40:54 PM

713[0JChecking patch project/plugins.sbt...

714Checking patch build.sbt...

715Applied patch project/plugins.sbt cleanly.

716Applied patch build.sbt cleanly.